Design and FPGA based implementation of barker demodulation block and CCK correlator block for DSSS technique in IEEE 802.11g (Record no. 10031)

000 -LEADER
fixed length control field 00586 a2200133 4500
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number -
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Shahnawaz Janjua
9 (RLIN) 93357
245 ## - TITLE STATEMENT
Title Design and FPGA based implementation of barker demodulation block and CCK correlator block for DSSS technique in IEEE 802.11g
Statement of responsibility, etc. Shahnawaz Janjua
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. Islamabad :
Name of publisher, distributor, etc. NUST School of Electrical Engineering & Computer Science,
Date of publication, distribution, etc. 2009.
300 ## - PHYSICAL DESCRIPTION
Extent 106 p. :
Other physical details ill. ;
Dimensions 27 cm +
Accompanying material CD-ROM
500 ## - GENERAL NOTE
General note Supervisors : Dr. N D Gohar, Mr. Bilal Saqib.
856 ## - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier <a href=" http://10.250.8.41:8080/xmlui/handle/123456789/29685"> http://10.250.8.41:8080/xmlui/handle/123456789/29685</a>
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Project Report
Call number prefix BICSE-3 SHA
Source of classification or shelving scheme
Holdings
Withdrawn status Lost status Damaged status Not for loan Permanent Location Current Location Date acquired Full call number Barcode Date last seen Price effective from Koha item type
WITHDRAWN       Central Library (CL) Central Library (CL) 07/04/2022 BICSE-3 SHA SEECSP00796 11/14/2012 11/14/2012 Project Report
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