| 000 -LEADER |
|---|
| fixed length control field |
02102 a2200277 4500 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
Nust |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20221130095607.0 |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
2004275960 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
047170055X |
| 040 ## - CATALOGING SOURCE |
|---|
| Transcribing agency |
Nust |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.38152,BAK |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Baker, R. Jacob, |
| 9 (RLIN) |
68300 |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
CMOS circuit design, layout, and simulation / |
| Statement of responsibility, etc. |
R. Jacob Baker. |
| 250 ## - EDITION STATEMENT |
|---|
| Edition statement |
2nd ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
New York : |
| Name of publisher, distributor, etc. |
IEEE Press, |
| Date of publication, distribution, etc. |
c2005. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xxxiii, 1038 p. : |
| Other physical details |
ill. ; |
| Dimensions |
25 cm. |
| 440 #0 - SERIES STATEMENT/ADDED ENTRY--TITLE |
|---|
| Title |
IEEE Press series on microelectronic systems |
| 9 (RLIN) |
99208 |
| 505 ## - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Introduction to CMOS Design (Page-1), The Well (Page-31), The Metal Layers (Page-59), The Active and Poly Layers (Page-83), Resistors, Capacitors, MOSFETs (Page-105), MOSFET Operation (Page-131), CMOS Fabrication by Jeff Jessing (Page-161), Electrical Noise: an overview (Page-213), Models for Analog Design (Page-269), Models for Digital Design (Page-311), The Inverter (Page-331), Static Logic Gates (Page-353), Clocked Circuits (Page-375), Dynamic Logic Gates (Page-397), VLSI Layout Examples (Page-411), Memory Circuits (Page-433), Sensing Using ?S Modulation (Page-483), Special Purpose CMOS Circuits (Page-523), Digital Phase-Locked Loops (Page-551), Current Mirrors (Page-613), Amplifiers (Page-657), Differential Amplifiers (Page-711), Voltage References (Page-745), Operational Amplifiers I (Page-773), Dynamic Analog Circuits (Page-829), Operational Amplifiers II (Page-863), Nonlinear Analog Circuits (Page-909), Data Converter Fundamentals (Page-931), Data Converter Architectures (Page-965). |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Telecommunication Engineering. |
| 710 2# - ADDED ENTRY--CORPORATE NAME |
|---|
| Corporate name or jurisdiction name as entry element |
Institute of Electrical and Electronics Engineers. |
| 9 (RLIN) |
25745 |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Book review (E-STREAMS) |
| Uniform Resource Identifier |
<a href="http://www.e-streams.com/es0902/es0902_4363.html">http://www.e-streams.com/es0902/es0902_4363.html</a> |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Contributor biographical information |
| Uniform Resource Identifier |
<a href="http://www.loc.gov/catdir/enhancements/fy0620/2004275960-b.html">http://www.loc.gov/catdir/enhancements/fy0620/2004275960-b.html</a> |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Publisher description |
| Uniform Resource Identifier |
<a href="http://www.loc.gov/catdir/enhancements/fy0620/2004275960-d.html">http://www.loc.gov/catdir/enhancements/fy0620/2004275960-d.html</a> |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Table of contents only |
| Uniform Resource Identifier |
<a href="http://www.loc.gov/catdir/enhancements/fy0620/2004275960-t.html">http://www.loc.gov/catdir/enhancements/fy0620/2004275960-t.html</a> |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Koha item type |
Book |
| Source of classification or shelving scheme |
|
