| 000 -LEADER |
|---|
| fixed length control field |
01593 a2200265 4500 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
Nust |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20170621102410.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
170621b xxu||||| |||| 00| 0 eng d |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
2003057671 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9812531319 |
| 040 ## - CATALOGING SOURCE |
|---|
| Transcribing agency |
RCMS |
| Original cataloging agency |
DLC |
| Language of cataloging |
DLC |
| 050 ## - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
621.392 PAD |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.392 PAD |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
T.R. Padmanabhan |
| 9 (RLIN) |
2988 |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Design through Verilog HDL |
| Statement of responsibility, etc. |
T.R. Padmanabhan, B. Bala Tripura Sundari. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
Singapore |
| Name of publisher, distributor, etc. |
IEEE Press ; |
| Place of publication, distribution, etc. |
Hoboken, NJ : |
| Name of publisher, distributor, etc. |
Wiley-Interscience, |
| Date of publication, distribution, etc. |
c2004. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xii, 455 p. : |
| Other physical details |
ill. ; |
| Dimensions |
25 cm. |
| 505 ## - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
1.introduction to VLSI design(page 1)2.introduction to verilog(page 11)3.language constructs and conventions in verilog (page 31)4.gate level modeling -1(page 47)5.gate level modeling -2 (page 81)6.modeling at data flow level(page 127)7.behavioral modeling -1(page 159)8.behavioral modeling 2(page 219)9.functions,tasks and user defined premitives(page 273)10.switch level modeling(page 305)11.system tasks,functions and compiler directives(page 339)12.queues,PLAS,and FSMS(page 407) |
| 538 ## - SYSTEM DETAILS NOTE |
|---|
| System details note |
Shelf # 09, Row # 1, History & Digital Design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Verilog (Computer hardware description language) |
| 9 (RLIN) |
2989 |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Tripura Sundari, B. Bala. |
| 9 (RLIN) |
2990 |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Contributor biographical information |
| Uniform Resource Identifier |
<a href="http://www.loc.gov/catdir/bios/wiley046/2003057671.html">http://www.loc.gov/catdir/bios/wiley046/2003057671.html</a> |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Publisher description |
| Uniform Resource Identifier |
<a href="http://www.loc.gov/catdir/description/wiley039/2003057671.html">http://www.loc.gov/catdir/description/wiley039/2003057671.html</a> |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Table of contents |
| Uniform Resource Identifier |
<a href="http://www.loc.gov/catdir/toc/wiley032/2003057671.html">http://www.loc.gov/catdir/toc/wiley032/2003057671.html</a> |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Koha item type |
Book |
| Classification part |
621.392 PAD |
