| 000 -LEADER |
|---|
| fixed length control field |
01607cam a2200325 a 4500 |
| 001 - CONTROL NUMBER |
|---|
| control field |
16996687 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
NUST |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20220722100316.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
111012s2013 njua 001 0 eng |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
2011039094 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
978-1-292-23116-7 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
DLC |
| Transcribing agency |
DLC |
| 042 ## - AUTHENTICATION CODE |
|---|
| Authentication code |
pcc |
| 050 00 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK7888.3 |
| Item number |
.M343 2013 |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.395, MAN |
| Edition number |
23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Mano, M. Morris, |
| Dates associated with a name |
1927- |
| 9 (RLIN) |
20186 |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Digital design : |
| Remainder of title |
with a introduction to the verilog hdl / |
| Statement of responsibility, etc. |
M. Morris Mano, Michael D. Ciletti. |
| 250 ## - EDITION STATEMENT |
|---|
| Edition statement |
6th ed. |
| Remainder of edition statement |
Global Edition |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
UK |
| Name of publisher, distributor, etc. |
Pearson Prentice Hall, |
| Date of publication, distribution, etc. |
2019. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
710 pages |
| Other physical details |
ill. ; |
| Dimensions |
25 cm. |
| 505 ## - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Chapter 1- Digital Systems and Binary Numbers (Page-17), Chapter 2- Boolean Algebra and Logic Gates (Page-57),Chapter 3- Gate-Level Minimization (Page-98),Chapter 4- Combinational Logic (Page-163),Chapter 5- Synchronous Sequential Logic (Page-261),Chapter 6- Registers and Counters (Page-342),Chapter 7- Memory and Programmable Logic (Page-393),Chapter 8- Design at the Register Transfer Level (Page-445),Chapter 9- Laboratory Experiments with Standard ICs and FPGAs (Page-571),Chapter 10- Standard Graphic Symbols (Page-621). |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Electronic digital computers |
| General subdivision |
Circuits. |
| 9 (RLIN) |
36507 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Logic circuits. |
| 9 (RLIN) |
17982 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Logic design. |
| 9 (RLIN) |
17983 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Digital integrated circuits. |
| 9 (RLIN) |
61563 |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Ciletti, Michael D. |
| 9 (RLIN) |
52068 |
| 906 ## - LOCAL DATA ELEMENT F, LDF (RLIN) |
|---|
| a |
7 |
| b |
cbc |
| c |
orignew |
| d |
1 |
| e |
ecip |
| f |
20 |
| g |
y-gencatlg |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Koha item type |
Book |
