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Towards automatic formal verification on generic combinational circuit using HOL

By: Sumayya Shiraz Material type: Text

TextPublisher: Islamabad NUST-SEECS 2014Description: 88 CD ROMDDC classification: MSEE-3 Online resources: Click here to access online

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Item type	Current location	Home library	Collection	Shelving location	Call number	Status	Date due	Barcode	Item holds
Thesis	Central Library (CL)	Central Library (CL)		Thesis	621.3MSEE-3 (Browse shelf)	Available		CL-T-4064
Project Report	Central Library (CL)	Central Library (CL)	NFIC	General Stacks	MSEE-3 (Browse shelf)	Available		SEECSP01588

Total holds: 0

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Previous	MSEE-3 Quantifying the multiple cognitive radio interfaces advantage.	MSEE-3 Capacity analysis of iptv over ieee 802.11n	MSEE-3 Physical device modelling and simulations of PHEMTS.	MSEE-3 Towards automatic formal verification on generic combinational circuit using HOL	MSEE-3 ALI Hardware software Co-design for optimal seam calculation	MSEE-3 ALI Nonlinear bayesian estimation of fMRI bold signal under non-gaussian noise	MSEE-3 AMI Analysis of strength of CAPTCHA schemes	Next

Supervisors:Dr. Osman Hasan, Dr. Muhammad Murtaza Khan, Dr. Rehan Hafiz, Dr. Amir Ali Khan

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