Design, simulation and testing of an 8-BIT processor using VHDL coding for CPLDs / GC Asad Rauf, GC Shahzad Hamid Javaid & GC Shahzaib Alam Khan , PC Malik Qasim Bashir and NC Hasan Shahzad Zaidi.
Publisher: Rawalpindi MCS 1999Description: 133 pSubject(s): UG Projects | TCC-6DDC classification: 621.382,RAU
Contents:
Design methodologies (Page-1) Programmable logic devices (Page-8) Hardware descriptive languages (Page-23) Levels of abstraction (Page-53) VHDL for design synthesis (Page-63) Processor design (Page-72) Our processor (Page-91) Software engineering and hardware implementation (Page-123).
| Item type | Current location | Home library | Shelving location | Call number | URL | Status | Notes | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|---|---|---|---|
Project Report
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Military College of Signals (MCS) | Military College of Signals (MCS) | Reference | 621.382, RAU (Browse shelf) | Link to resource | Available | Almirah No. 94, Shelf No. 1 | MCSPTC-20 |
Total holds: 0
Design methodologies (Page-1) Programmable logic devices (Page-8) Hardware descriptive languages (Page-23) Levels of abstraction (Page-53) VHDL for design synthesis (Page-63) Processor design (Page-72) Our processor (Page-91) Software engineering and hardware implementation (Page-123).
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