Computer architecture : a quantitative approach / John L. Hennessy, David A. Patterson ; with contributions by Andrea C. Arpaci-Dusseau ... [et al.].
Publisher: Amsterdam ; Boston : Morgan Kaufmann, 2007Edition: 4th edDescription: 1 v. (various pagings) : ill. ; 24 cm. + 1 CD-ROM (4 3/4 in.)ISBN: 0123704901 (pbk. : alk. paper); 9780123704900Subject(s): Computer architectureDDC classification: 004.22,HEN Online resources: Publisher description | Table of contents only
Contents:
fundamentals of Computer Design (Page-1), Instruction Level Parallelism and its Exploitation (Page-66), Limits on Instruction-Level Parallelism (Page-154), Multiprocessors and Thread-Level Parallelism (Page-196),Memory Hierarchy Design (Page-288). Storage Systems (Page-358), APPENDIX A: Pipelining: Basic and Intermediate Concepts (Page A-2), APPENDIX B: Instruction Set Principles and Examples (Page B-2), APPENDIX C: Instruction Set Principles and Examples (Page C-2).
| Item type | Current location | Home library | Shelving location | Call number | URL | Status | Notes | Date due | Barcode | Item holds |
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Military College of Signals (MCS) | Military College of Signals (MCS) | General Stacks | 004.22,HEN (Browse shelf) | Available | Almirah No.2, Self No.3 | MCS33774 | |||
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Book
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Military College of Signals (MCS) | Military College of Signals (MCS) | General Stacks | 004.22,HEN (Browse shelf) | Link to resource | Available | Almirah No.2, Self No.3 | MCS36406 |
Total holds: 0
fundamentals of Computer Design (Page-1), Instruction Level Parallelism and its Exploitation (Page-66), Limits on Instruction-Level Parallelism (Page-154), Multiprocessors and Thread-Level Parallelism (Page-196),Memory Hierarchy Design (Page-288). Storage Systems (Page-358), APPENDIX A: Pipelining: Basic and Intermediate Concepts (Page A-2), APPENDIX B: Instruction Set Principles and Examples (Page B-2), APPENDIX C: Instruction Set Principles and Examples (Page C-2).
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