Design through Verilog HDL T.R. Padmanabhan, B. Bala Tripura Sundari.
Publisher: Singapore Hoboken, NJ : IEEE Press ; Wiley-Interscience, c2004Description: xii, 455 p. : ill. ; 25 cmISBN: 9812531319Subject(s): Verilog (Computer hardware description language)DDC classification: 621.392 PAD LOC classification: 621.392 PADOnline resources: Contributor biographical information | Publisher description | Table of contents| Item type | Current location | Home library | Shelving location | Call number | Status | Date due | Barcode | Item holds |
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Central Library (CL) | Central Library (CL) | General Stacks | 621.392 (Browse shelf) | Available | RCMS000134 | ||
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NUST Baluchistan Campus (NBC) | NUST Baluchistan Campus (NBC) | General Stacks | 621.392 (Browse shelf) | Available | RCMS000135 | ||
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NUST Baluchistan Campus (NBC) | NUST Baluchistan Campus (NBC) | General Stacks | 621.392 (Browse shelf) | Available | RCMS000964 | ||
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NUST Baluchistan Campus (NBC) | NUST Baluchistan Campus (NBC) | General Stacks | 621.392 (Browse shelf) | Available | RCMS000965 | ||
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NUST Baluchistan Campus (NBC) | NUST Baluchistan Campus (NBC) | General Stacks | 621.392 (Browse shelf) | Available | RCMS000136 | ||
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NUST Baluchistan Campus (NBC) | NUST Baluchistan Campus (NBC) | General Stacks | 621.392 (Browse shelf) | Available | RCMS000137 |
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| 621.3916 ASH Digital design: an embedded systems approach using VHDL | 621.3916 CAT Designing embedded hardware | 621.3916076 GRO A+ Core Module study guide | 621.392 Design through Verilog HDL | 621.392 ASH The system designer's guide to VHDL-AMS: analog, mixed-signal, and mixed-technology modeling | 621.392 BHA A VHDL primer | 621.392 BHA A VHDL primer |
1.introduction to VLSI design(page 1)2.introduction to verilog(page 11)3.language constructs and conventions in verilog (page 31)4.gate level modeling -1(page 47)5.gate level modeling -2 (page 81)6.modeling at data flow level(page 127)7.behavioral modeling -1(page 159)8.behavioral modeling 2(page 219)9.functions,tasks and user defined premitives(page 273)10.switch level modeling(page 305)11.system tasks,functions and compiler directives(page 339)12.queues,PLAS,and FSMS(page 407)
Shelf # 09, Row # 1, History & Digital Design.
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