NUST Institutions Library Catalogue

Verilog HDL: a guide to digital design and synthesis a guide to digital design and synthesis Samir Palnitkar

By: Palnitkar, SamirPublisher: Upper Saddle River, NJ : SunSoft Press, c2003Edition: 2nd edDescription: xlii, 490 p. : ill. ; 25 cm. +ISBN: 8129700921Subject(s): Verilog (Computer hardware description language)DDC classification: 621.392
Contents:
Pt. 1. Basic Verilog Topics -- 1. Overview of Digital Design with Verilog HDL -- 2. Hierarchical Modeling Concepts -- 3. Basic Concepts -- 4. Modules and Ports -- 5. Gate-Level Modeling -- 6. Dataflow Modeling -- 7. Behavioral Modeling -- 8. Tasks and Functions -- 9. Useful Modeling Techniques -- Pt. 2. Advanced Verilog Topics -- 10. Timing and Delays -- 11. Switch-Level Modeling -- 12. User-Defined Primitives -- 13. Programming Language Interface -- 14. Logic Synthesis with Verilog HDL -- 15. Advanced Verification Techniques -- Pt. 3. Appendices -- App. A. Strength Modeling and Advanced Net Definitions -- App. B. List of PLI Routines -- App. C. List of Keywords, System Tasks, and Compiler Directives -- App. D. Formal Syntax Definition -- App. E. Verilog Tidbits -- App. F. Verilog Examples.
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Item type Current location Home library Collection Shelving location Call number Status Date due Barcode Item holds
Book Book Central Library (CL)
Central Library (CL)
NFIC General Stacks 621.392 PAL (Browse shelf) Checked out 05/06/2026 SEECSD00948
Book Book Central Library (CL)
Central Library (CL)
NFIC General Stacks 621.392 PAL (Browse shelf) Available SEECS007184
Book Book Central Library (CL)
Central Library (CL)
NFIC General Stacks 621.392 PAL (Browse shelf) Checked out 05/23/2024 SEECS004742
Total holds: 0

"A Prentice Hall title."

"Professional technical reference"--P. [4] cover.

Pt. 1. Basic Verilog Topics -- 1. Overview of Digital Design with Verilog HDL -- 2. Hierarchical Modeling Concepts -- 3. Basic Concepts -- 4. Modules and Ports -- 5. Gate-Level Modeling -- 6. Dataflow Modeling -- 7. Behavioral Modeling -- 8. Tasks and Functions -- 9. Useful Modeling Techniques -- Pt. 2. Advanced Verilog Topics -- 10. Timing and Delays -- 11. Switch-Level Modeling -- 12. User-Defined Primitives -- 13. Programming Language Interface -- 14. Logic Synthesis with Verilog HDL -- 15. Advanced Verification Techniques -- Pt. 3. Appendices -- App. A. Strength Modeling and Advanced Net Definitions -- App. B. List of PLI Routines -- App. C. List of Keywords, System Tasks, and Compiler Directives -- App. D. Formal Syntax Definition -- App. E. Verilog Tidbits -- App. F. Verilog Examples.

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