A top down constraint driven design methodology for analog integrated circuits
Material type:
TextPublisher: BOSTON KLUWER 1997Description: 369PISBN: 0-7923-9794-0DDC classification: 621.392 CHA'T
| Item type | Current location | Home library | Shelving location | Call number | Status | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|---|---|
Book
|
College of Electrical & Mechanical Engineering (CEME) | College of Electrical & Mechanical Engineering (CEME) | General Stacks | 621.392 CHA'T (Browse shelf) | Available | CEME-30385 |
Total holds: 0
Browsing College of Electrical & Mechanical Engineering (CEME) shelves, Shelving location: General Stacks Close shelf browser
| 621.392 BHA'V A vhdl primer based on ieee standard 1076 - 1993 | 621.392 BRO Fundamentals of digital logic with verilog design | 621.392 BRO Fundamentals of Digital Logic with Verilog Design | 621.392 CHA'T A top down constraint driven design methodology for analog integrated circuits | 621.392 HAY Computer architecture and organization | 621.392 JER Behavioral synthesis and component reuse with vhdl | 621.392 LIM Vhdl a design oriented approach |
There are no comments on this title.