Nirmal Saeed <br/><br/>
V-Holt Verifier (A formal verification tool for combinational circuits) 
Nirmal Saeed 
 - Islamabad  NUST-SEECS  2012 
 - 72p.  ;ill.  ;27cm.+  CD ROM 
<br/><br/> Supervisors: Dr. Osma Hasan, Dr. M. Murtaza Khan 
<br/><br/> HB 
<br/><br/><label>Dewey Class. No.: </label>BEE-5