Switch-level timing simulation of MOS VLSI circuits / 
by Vasant B. Rao ... [et al.]. 
 - Boston :  Kluwer Academic Publishers,  c1989. 
 - x, 209 p. :  ill. ;  25 cm. 
 - The Kluwer international series in engineering and computer science ;  VSLI, computer architecture and digital signal processing  SECS 66. .
 - Kluwer international series in engineering and computer science ; Kluwer international series in engineering and computer science. .
<br/><br/>Introduction (Page-1), Overview Simulation Techniques (Page-7), MOS Network Partitioning and Ordering (Page-27), Switch Level  Timing Simulation (Page-93), Simulating Strongly Connected Components (Page-163). 
<br/><br/><label>ISBN: </label>0898383021 
<br/><br/><label>LCCN: </label>88030591 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Telecommunication Engineering.
<br/><br/><label>Dewey Class. No.: </label>621.381730724,RAD