01011    a2200205   4500003000500000005001700005010001600022020001500038040000900053082002200062245009000084260005000174300003200224490014300256505021300399650003500612700001900647830007000666830006900736Nust20220815093111.0  a   88030591  a0898383021  cNust00a621.381730724,RAD00aSwitch-level timing simulation of MOS VLSI circuits /cby Vasant B. Rao ... [et al.].  aBoston :bKluwer Academic Publishers,cc1989.  ax, 209 p. :bill. ;c25 cm.1 aThe Kluwer international series in engineering and computer science ;vSECS 66.aVSLI, computer architecture and digital signal processing  aIntroduction (Page-1), Overview Simulation Techniques (Page-7), MOS Network Partitioning and Ordering (Page-27), Switch Level  Timing Simulation (Page-93), Simulating Strongly Connected Components (Page-163). 0aTelecommunication Engineering.1 aRao, Vasant B. 0aKluwer international series in engineering and computer science ; 0aKluwer international series in engineering and computer science.