01088 a2200229 4500 Nust 20220815093111.0 88030591 0898383021 Nust 621.381730724,RAD Switch-level timing simulation of MOS VLSI circuits / by Vasant B. Rao ... [et al.]. Boston : Kluwer Academic Publishers, c1989. x, 209 p. : ill. ; 25 cm. The Kluwer international series in engineering and computer science ; SECS 66. VSLI, computer architecture and digital signal processing Introduction (Page-1), Overview Simulation Techniques (Page-7), MOS Network Partitioning and Ordering (Page-27), Switch Level Timing Simulation (Page-93), Simulating Strongly Connected Components (Page-163). Telecommunication Engineering. Rao, Vasant B. 97084 Kluwer international series in engineering and computer science ; 82222 Kluwer international series in engineering and computer science. 82222 REF ddc 175766 175766 0 0 ddc 0 0 MCS MCS REF 2016-12-12 621.381730724,RAD MCS801 2016-12-08 2016-12-12 REF Almirah No.21, Shelf No.5