Switch-level timing simulation of MOS VLSI circuits

Switch-level timing simulation of MOS VLSI circuits Rao, Vasant B. Boston Kluwer Academic Publishers c1989 x, 209 p. : ill. ; 25 cm. Introduction (Page-1), Overview Simulation Techniques (Page-7), MOS Network Partitioning and Ordering (Page-27), Switch Level Timing Simulation (Page-93), Simulating Strongly Connected Components (Page-163). by Vasant B. Rao ... [et al.]. Telecommunication Engineering 621.381730724,RAD Kluwer international series in engineering and computer science Kluwer international series in engineering and computer science 0898383021 88030591 20220815093111.0