TY  - GEN
AU  - Rao,Vasant B.
TI  - Switch-level timing simulation of MOS VLSI circuits
T2  - The Kluwer international series in engineering and computer science
SN  - 0898383021
U1  - 621.381730724,RAD 
PY  - 1989///
CY  - Boston
PB  - Kluwer Academic Publishers
KW  - Telecommunication Engineering
N1  - Introduction (Page-1), Overview Simulation Techniques (Page-7), MOS Network Partitioning and Ordering (Page-27), Switch Level  Timing Simulation (Page-93), Simulating Strongly Connected Components (Page-163)
ER  -