01653 a2200277 4500 Nust 20221129161303.0 98006335 8186308733 Nust 621.3815,INT Integrated circuit manufacturability : the art of process and design integration / edited by Jos⥠Pineda de Gyvez, Dhiraj Pradhan. Piscataway, NJ : IEEE Press ; New York : Institute of Electrical and Electronics Engineers, c1999. xv, 316 p. : ill. ; 26 cm. Introduction (Page-1), Defect Monitoring And Characterization (Page-9), Digital CMOS Fault Modeling And Inductive Fault Analysis (Page-43), Functional Yield Modeling (Page-85), Critical Area And Fault Probability Prediction (Page-121), Statistical Methods Of Parametric Yield And Quality Enhancement (Page-157), Architectural Fault Tolerance (Page-217), Design For Test And Manufacturability (Page-269), Testing Solutions For MCM Manufacturing (Page-287). Integrated circuits Testing. 103765 Metal oxide semiconductors, Complementary Computer-aided design. 103794 Telecommunication engineering Pineda de Gyvez, Jos⥮ 103795 Pradhan, Dhiraj K. 103796 IEEE Circuits and Systems Society. 103691 Contributor biographical information http://www.loc.gov/catdir/bios/wiley044/98006335.html Publisher description http://www.loc.gov/catdir/description/wiley037/98006335.html Table of Contents http://www.loc.gov/catdir/toc/onix07/98006335.html REF ddc 178593 178593 0 0 ddc 0 0 MCS MCS GEN 2016-12-12 621.3815,INT MCS32607 2016-12-08 2016-12-12 BK Almirah No.33, Shelf No.1