the art of process and design integration Pineda de Gyvez, Jos⥮ Pradhan, Dhiraj K. IEEE Circuits and Systems Society Piscataway, NJ New York IEEE Press Institute of Electrical and Electronics Engineers c1999 xv, 316 p. : ill. ; 26 cm. Introduction (Page-1), Defect Monitoring And Characterization (Page-9), Digital CMOS Fault Modeling And Inductive Fault Analysis (Page-43), Functional Yield Modeling (Page-85), Critical Area And Fault Probability Prediction (Page-121), Statistical Methods Of Parametric Yield And Quality Enhancement (Page-157), Architectural Fault Tolerance (Page-217), Design For Test And Manufacturability (Page-269), Testing Solutions For MCM Manufacturing (Page-287). edited by Jos⥠Pineda de Gyvez, Dhiraj Pradhan. Integrated circuits Testing Metal oxide semiconductors, Complementary Computer-aided design Telecommunication engineering 621.3815,INT 8186308733 98006335 http://www.loc.gov/catdir/bios/wiley044/98006335.html http://www.loc.gov/catdir/description/wiley037/98006335.html http://www.loc.gov/catdir/toc/onix07/98006335.html http://www.loc.gov/catdir/bios/wiley044/98006335.html http://www.loc.gov/catdir/description/wiley037/98006335.html http://www.loc.gov/catdir/toc/onix07/98006335.html 20221129161303.0