TY  - GEN
AU  - 
AU  - 
ED  - IEEE Circuits and Systems Society.
TI  - Integrated circuit manufacturability: the art of process and design integration 
SN  - 8186308733
U1  - 621.3815,INT 
PY  - 1999///
CY  - Piscataway, NJ, New York
PB  - IEEE Press, Institute of Electrical and Electronics Engineers
KW  - Integrated circuits
KW  - Testing
KW  - Metal oxide semiconductors, Complementary
KW  - Computer-aided design
KW  - Telecommunication engineering
N1  - Introduction (Page-1), Defect Monitoring And Characterization (Page-9), Digital CMOS Fault Modeling And Inductive Fault Analysis (Page-43), Functional Yield Modeling (Page-85), Critical Area And Fault Probability Prediction (Page-121), Statistical Methods Of Parametric Yield And Quality Enhancement (Page-157), Architectural Fault Tolerance (Page-217), Design For Test And Manufacturability (Page-269), Testing Solutions For MCM Manufacturing (Page-287)
UR  - http://www.loc.gov/catdir/bios/wiley044/98006335.html
UR  - http://www.loc.gov/catdir/description/wiley037/98006335.html
UR  - http://www.loc.gov/catdir/toc/onix07/98006335.html
ER  -