01791 a2200289 4500003000500000005001700005010001600022020001500038040000900053082001700062245013800079260010700217300003300324505046000357650004200817650007800859650003400937700003600971700003101007710004701038856009601085856008801181856007401269942001301343999001901356952012601375Nust20221129161303.0 a 98006335 a8186308733 cNust00a621.3815,INT00aIntegrated circuit manufacturability :bthe art of process and design integration /cedited by Josā„ Pineda de Gyvez, Dhiraj Pradhan. aPiscataway, NJ :bIEEE Press ;aNew York :bInstitute of Electrical and Electronics Engineers,cc1999. axv, 316 p. :bill. ;c26 cm. aIntroduction (Page-1), Defect Monitoring And Characterization (Page-9), Digital CMOS Fault Modeling And Inductive Fault Analysis (Page-43), Functional Yield Modeling (Page-85), Critical Area And Fault Probability Prediction (Page-121), Statistical Methods Of Parametric Yield And Quality Enhancement (Page-157), Architectural Fault Tolerance (Page-217), Design For Test And Manufacturability (Page-269), Testing Solutions For MCM Manufacturing (Page-287). 0aIntegrated circuitsxTesting.9103765 0aMetal oxide semiconductors, ComplementaryxComputer-aided design.9103794 0aTelecommunication engineering2 aPineda de Gyvez, Josā„®91037952 aPradhan, Dhiraj K.91037962 aIEEE Circuits and Systems Society.9103691423Contributor biographical informationuhttp://www.loc.gov/catdir/bios/wiley044/98006335.html423Publisher descriptionuhttp://www.loc.gov/catdir/description/wiley037/98006335.html423Table of Contentsuhttp://www.loc.gov/catdir/toc/onix07/98006335.html cREF2ddc c178593d178593 00102ddc4070aMCSbMCScGENd2016-12-12o621.3815,INTpMCS32607r2016-12-08w2016-12-12yBKzAlmirah No.33, Shelf No.1