TY  - GEN
AU  - Zwolinki,Mark
TI  - Digital system design with VHDL
SN  - 8129706504
U1  - 621.38121,ZWO 
PY  - 2000///
CY  - Harlow, England, New York
PB  - Prentice Hall
KW  - Digital electronics
KW  - Data processing
KW  - Telecommunication Engineering
N1  - Introduction (Page-1), Combinational Logic Design (Page-19), Combinational Logic Using VHDL Gate Models (Page-38), Combinational Building Blocks (Page-53), Synchronous Sequential Design (Page-80), VHDL Models of Sequential Blocks (Page-115), VHDL Simulation (Page-178), VHDL  Synthesis (Page-190), Testing Digital Systems (Page-221), Design for Testability (Page-248), Asynchronous Sequential Design (Page-271), Interfacing with the Analogue World (Page-301).
ER  -