For VLSI design Layout & Test Automation Mazumder,Pinaki creator India Pearson Education 1999 ix, 338 p. : ill. ; 24 cm. Introduction (Page-1), Partitioning (Page-37), Standard cell and macro cell placement (Page-69), Macro cell routing (Page-107), FPGA technology mapping (Page-140), Automatic test generation (Page-158), Peak power estimation (Page-227), Parallel implementations (Page-252), Conclusion (Page-295), Glossary (Page-305). Pinaki Mazumder Genetic algorithms Investment analysis Mathematical models Investments Mathematical models 519,MAZ 0471576794 93011984 http://www.loc.gov/catdir/bios/wiley044/93011984.html http://www.loc.gov/catdir/description/wiley037/93011984.html http://www.loc.gov/catdir/toc/onix03/93011984.html http://www.loc.gov/catdir/bios/wiley044/93011984.html http://www.loc.gov/catdir/description/wiley037/93011984.html http://www.loc.gov/catdir/toc/onix03/93011984.html 20221122123639.0