01224    a2200217   4500003000500000005001700005010001600022020001500038040000900053082001700062100002100079245010700100260003100207300003500238505049500273650003400768700002400802700001800826856008800844856007400932Nust20221125143035.0  a   87023013  a0471624632  cNust00a621.3815,BAR1 aBardell, Paul H.10aBuilt-in test for VLSI :bpseudorandom techniques /cPaul H. Bardell, William H. McAnney, Jacob Savir.  aNew York :bWiley,cc1987.  axiii, 354 p. :bill. ;c24 cm.  aDigital Testing and the Need for Testable (Page-1), Introduction to Testable Design (Page-17), Pseudorandom Sequence Generators (Page-61), Test Response Compression Techniques (Page-89), Shift Register Polynomial Division (Page-109), Special Purpose Shift Register Circuits (Page-145), Random Pattern Built-in Test (Page-177), Built –in Test Structures (Page-279), Limitations and other Concerns of Random Pattern Testing (Page-314), Test System Requirements for Built-In Test (Page-311). 0aTelecommunication engineering1 aMcAnney, William H.1 aSavir, Jacob.423Publisher descriptionuhttp://www.loc.gov/catdir/description/wiley033/87023013.html423Table of Contentsuhttp://www.loc.gov/catdir/toc/onix04/87023013.html