Touheed , Hassaan NC   (TCC-9) <br/><br/>
Development of verification and debugging tool for RTL codes in Verilog HDL using co-simulation with C language model / 
Hassaan Touheed ,NC  Muhammad Afzal Malik  , GC Umar Farooq and PC Abbas Ali Mirza 
 - Rawalpindi  MCS (NUST)  2001 
 - 61p.; 
<br/><br/>Introduction (Page-7), Digital System Design in Hardware Description Language (Page-9), Hardware Modelling in Programming Language (Page-17),  The Sockets API (Page-19), Verilog PLI (Page-23), PLI Routing in Verilog Stimulus (Page-25), PLI Interface in C (Page-32), Using the Routines (page-35), C Functions Behind PLI Routines (Page-40), Cosimulation for Media Engine 0 (Page-44), RLT Debugging and Verification Environment for Micro Engines (Page-50).    
<br/><br/><label>Subjects--Topical Terms: </label><br/>UG Projects
<br/><br/><label>Subjects--Geographic Terms: </label><br/>TCC-9
<br/><br/><label>Dewey Class. No.: </label>621.382,TOU