TY  - GEN
AU  - Touheed , Hassaan NC   (TCC-9)
AU  - Supervised by Maj (R) Fazal Ahmed
TI  - Development of verification and debugging tool for RTL codes in Verilog HDL using co-simulation with C language model
U1  - 621.382,TOU 
PY  - 2001///
CY  - Rawalpindi
PB  - MCS (NUST)
KW  - UG Projects
KW  - TCC-9
N1  - Introduction (Page-7), Digital System Design in Hardware Description Language (Page-9), Hardware Modelling in Programming Language (Page-17),  The Sockets API (Page-19), Verilog PLI (Page-23), PLI Routing in Verilog Stimulus (Page-25), PLI Interface in C (Page-32), Using the Routines (page-35), C Functions Behind PLI Routines (Page-40), Cosimulation for Media Engine 0 (Page-44), RLT Debugging and Verification Environment for Micro Engines (Page-50).
ER  -