Rauf, GC Asad (TCC-6) <br/><br/>
Design, simulation and testing of an 8-BIT processor using VHDL coding for CPLDs /  GC Asad Rauf, GC Shahzad Hamid Javaid & GC Shahzaib Alam Khan , PC Malik Qasim Bashir and NC Hasan Shahzad Zaidi.  

 - Rawalpindi  MCS  1999 
 - 133 p.; 
<br/><br/>Design methodologies (Page-1)  Programmable logic devices (Page-8) Hardware descriptive languages (Page-23) Levels of abstraction (Page-53) VHDL for design synthesis (Page-63) Processor design (Page-72) Our processor (Page-91)  Software engineering and hardware implementation (Page-123). 
<br/><br/><label>Subjects--Topical Terms: </label><br/>UG Projects
<br/><br/><label>Subjects--Geographic Terms: </label><br/>TCC-6
<br/><br/><label>Dewey Class. No.: </label>621.382,RAU