TY  - GEN
AU  - Rauf, GC Asad (TCC-6)
AU  - Supervised by Lt Col Dr. Ashraf Masood
TI  - Design, simulation and testing of an 8-BIT processor using VHDL coding for CPLDs: GC Asad Rauf, GC Shahzad Hamid Javaid & GC Shahzaib Alam Khan , PC Malik Qasim Bashir and NC Hasan Shahzad Zaidi. 
U1  - 621.382,RAU 
PY  - 1999///
CY  - Rawalpindi
PB  - MCS
KW  - UG Projects
KW  - TCC-6
N1  - Design methodologies (Page-1)  Programmable logic devices (Page-8) Hardware descriptive languages (Page-23) Levels of abstraction (Page-53) VHDL for design synthesis (Page-63) Processor design (Page-72) Our processor (Page-91)  Software engineering and hardware implementation (Page-123)
ER  -