TY  - GEN
AU  - Yanushkevich,Svetlana N.
AU  - Lyshevski,Sergey Edward
AU  - Shmerko,Vlad P.
TI  - Logic design of nanoICs
SN  - 0-8493-2766-0 (alk. paper)
U1  - 621.381,YAN 
PY  - 2005///
CY  - Baco Raton, FL
PB  - CRC Press
KW  - Telecommunication Engineering
N1  - Introduction (Page-1), Nanotechnologies (Page-27), Basics of Logic Design in Nano space (Page-65),  Word-Level Data Structures (Page-117),  Nano space and Hypercube-Like Data Structures (Page-151), Nan dimensional Multilevel Circuits (Page-187), Linear Word-Level Models of Multilevel Circuits (Page-211), Event-Driven Analysis of Hypercube-Like Topology (Page-255), Nan dimensional Multivalve Circuits (Page-301),   Parallel Computation in Nanospace (Page-359), Fault-Tolerant Computation (Page-385), Information Measures in Nan dimensions (Page-411)
ER  -