TY  - GEN
AU  - Hennessy,John L.
AU  - Arpaci-Dusseau,Andrea C.
AU  - Patterson,David A.
TI  - Computer architecture: a quantitative approach 
SN  - 0123704901 (pbk. : alk. paper)
U1  - 004.22,HEN 
PY  - 2007///
CY  - Amsterdam, Boston
PB  - Morgan Kaufmann
KW  - Computer architecture
N1  - fundamentals of Computer Design (Page-1), Instruction Level Parallelism and its Exploitation (Page-66), Limits on Instruction-Level Parallelism (Page-154), Multiprocessors and Thread-Level Parallelism (Page-196),Memory Hierarchy Design (Page-288). Storage Systems (Page-358), APPENDIX A: Pipelining: Basic and Intermediate Concepts (Page A-2), APPENDIX B: Instruction Set Principles and Examples (Page B-2), APPENDIX C: Instruction Set Principles and Examples (Page C-2)
UR  - http://www.loc.gov/catdir/enhancements/fy0665/2006024358-d.html
UR  - http://www.loc.gov/catdir/toc/ecip0618/2006024358.html
ER  -