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  <titleInfo>
    <title>Digital systems design with VHDL and synthesis</title>
    <subTitle>an integrated approach</subTitle>
  </titleInfo>
  <name type="personal">
    <namePart>Chang, K.C</namePart>
    <role>
      <roleTerm authority="marcrelator" type="text">creator</roleTerm>
    </role>
  </name>
  <typeOfResource/>
  <originInfo>
    <place>
      <placeTerm type="text">Washington</placeTerm>
    </place>
    <publisher>IEEE computer society</publisher>
    <dateIssued>1999</dateIssued>
    <issuance/>
  </originInfo>
  <physicalDescription>
    <extent>499p</extent>
  </physicalDescription>
  <tableOfContents>Introduction (Page-1), VHDL and digital circuit primitives (Page-4), VHDL simulation and synthesis environment and design process (Page-32), Basic combinational circuits (Page-53), Basic binary arithmetic circuits (Page-91), Basic sequential circuits (Page-143), Registers (Page-187), Clock and reset circuits (Page-222), Dual port ram,fifo and dram modeling (Page-251), A design case study :finite impulse response filter asic design (Page-288), A design case study a microprogram controller design (Page-341),,Error detection and correction (Page-390), Fixed point multiplication (Page-408), Ffixed point division (Page-445), Floating -point arithmetic (Page-467).</tableOfContents>
  <note type="statement of responsibility">K.C.Chang</note>
  <subject>
    <topic>Digital systems design with VHDL and synthesis</topic>
  </subject>
  <classification authority="ddc">621.392,CHA</classification>
  <identifier type="isbn">9812531610</identifier>
  <identifier type="lccn">9924750</identifier>
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    <recordChangeDate encoding="iso8601">20221226110428.0</recordChangeDate>
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