T.R. Padmanabhan  <br/><br/>
Design through Verilog HDL 
T.R. Padmanabhan, B. Bala Tripura Sundari. 
 - Singapore  Hoboken, NJ :  IEEE Press ;  Wiley-Interscience,  c2004. 
 - xii, 455 p. :  ill. ;  25 cm. 
<br/><br/>1.introduction to VLSI design(page 1)2.introduction to verilog(page 11)3.language constructs and conventions in verilog (page 31)4.gate level modeling -1(page 47)5.gate level modeling -2 (page 81)6.modeling at data flow level(page 127)7.behavioral modeling -1(page 159)8.behavioral modeling 2(page 219)9.functions,tasks and user defined premitives(page 273)10.switch level modeling(page 305)11.system tasks,functions and compiler directives(page 339)12.queues,PLAS,and FSMS(page 407) 
<br/><br/><br/>Shelf # 09, Row # 1, History & Digital Design. 
<br/><br/><label>ISBN: </label>9812531319 
<br/><br/><label>LCCN: </label>2003057671 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Verilog (Computer hardware description language)
<br/><br/><label>LC Class. No.: </label>621.392 PAD 
<br/><br/><label>Dewey Class. No.: </label>621.392 PAD