01593 a2200265 4500 23277 23277 Nust 20170621102410.0 170621b xxu||||| |||| 00| 0 eng d 2003057671 9812531319 RCMS DLC DLC 621.392 PAD 621.392 PAD T.R. Padmanabhan 2988 Design through Verilog HDL T.R. Padmanabhan, B. Bala Tripura Sundari. Singapore IEEE Press ; Hoboken, NJ : Wiley-Interscience, c2004. xii, 455 p. : ill. ; 25 cm. 1.introduction to VLSI design(page 1)2.introduction to verilog(page 11)3.language constructs and conventions in verilog (page 31)4.gate level modeling -1(page 47)5.gate level modeling -2 (page 81)6.modeling at data flow level(page 127)7.behavioral modeling -1(page 159)8.behavioral modeling 2(page 219)9.functions,tasks and user defined premitives(page 273)10.switch level modeling(page 305)11.system tasks,functions and compiler directives(page 339)12.queues,PLAS,and FSMS(page 407) Shelf # 09, Row # 1, History & Digital Design. Verilog (Computer hardware description language) 2989 Tripura Sundari, B. Bala. 2990 Contributor biographical information http://www.loc.gov/catdir/bios/wiley046/2003057671.html Publisher description http://www.loc.gov/catdir/description/wiley039/2003057671.html Table of contents http://www.loc.gov/catdir/toc/wiley032/2003057671.html ddc BK 621.392 PAD 0 0 0 0 NQC NQC GEN 2013-03-07 621.392 RCMS000135 2015-09-08 2013-03-07 BK 0 0 0 0 NQC NQC GEN 2013-03-07 1 621.392 RCMS000964 2019-09-19 2019-09-19 2013-03-07 BK 0 0 0 0 NQC NQC GEN 2013-03-07 621.392 RCMS000965 2013-03-07 2013-03-07 BK 0 0 0 0 NQC NQC GEN 2013-03-07 621.392 RCMS000136 2013-03-07 2013-03-07 BK 0 0 0 0 NQC NQC GEN 2013-03-07 621.392 RCMS000137 2013-03-07 2013-03-07 BK 0 0 0 0 CL CL GEN 2014-04-24 1 621.392 RCMS000134 2014-09-05 2014-09-05 2014-04-24 BK