Design through Verilog HDL

Design through Verilog HDL T.R. Padmanabhan creator Tripura Sundari, B. Bala. xxu Singapore Hoboken, NJ IEEE Press Wiley-Interscience c2004 eng xii, 455 p. : ill. ; 25 cm. 1.introduction to VLSI design(page 1)2.introduction to verilog(page 11)3.language constructs and conventions in verilog (page 31)4.gate level modeling -1(page 47)5.gate level modeling -2 (page 81)6.modeling at data flow level(page 127)7.behavioral modeling -1(page 159)8.behavioral modeling 2(page 219)9.functions,tasks and user defined premitives(page 273)10.switch level modeling(page 305)11.system tasks,functions and compiler directives(page 339)12.queues,PLAS,and FSMS(page 407) T.R. Padmanabhan, B. Bala Tripura Sundari. Shelf # 09, Row # 1, History & Digital Design. Verilog (Computer hardware description language) 621.392 PAD 621.392 PAD 9812531319 2003057671 http://www.loc.gov/catdir/bios/wiley046/2003057671.html http://www.loc.gov/catdir/description/wiley039/2003057671.html http://www.loc.gov/catdir/toc/wiley032/2003057671.html http://www.loc.gov/catdir/bios/wiley046/2003057671.html http://www.loc.gov/catdir/description/wiley039/2003057671.html http://www.loc.gov/catdir/toc/wiley032/2003057671.html DLC 170621 20170621102410.0 DLC