Palnitkar, Samir. <br/><br/>
Verilog HDL: a guide to digital design and synthesis  a guide to digital design and synthesis  
Samir Palnitkar 
 - 2nd ed. 
 - Upper Saddle River, NJ :  SunSoft Press,  c2003. 
 - xlii, 490 p. :  ill. ;  25 cm. + 
<br/><br/> "A Prentice Hall title."  "Professional technical reference"--P. [4] cover. 
<br/><br/>Pt. 1. Basic Verilog Topics -- 1. Overview of Digital Design with Verilog HDL -- 2. Hierarchical Modeling Concepts -- 3. Basic Concepts -- 4. Modules and Ports -- 5. Gate-Level Modeling -- 6. Dataflow Modeling -- 7. Behavioral Modeling -- 8. Tasks and Functions -- 9. Useful Modeling Techniques -- Pt. 2. Advanced Verilog Topics -- 10. Timing and Delays -- 11. Switch-Level Modeling -- 12. User-Defined Primitives -- 13. Programming Language Interface -- 14. Logic Synthesis with Verilog HDL -- 15. Advanced Verification Techniques -- Pt. 3. Appendices -- App. A. Strength Modeling and Advanced Net Definitions -- App. B. List of PLI Routines -- App. C. List of Keywords, System Tasks, and Compiler Directives -- App. D. Formal Syntax Definition -- App. E. Verilog Tidbits -- App. F. Verilog Examples. 
<br/><br/><label>ISBN: </label>8129700921 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Verilog (Computer hardware description language)
<br/><br/><label>Dewey Class. No.: </label>621.392