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  <titleInfo>
    <title>VeriIog HDL: digital design and modeling</title>
    <subTitle>digital design and modeling</subTitle>
  </titleInfo>
  <name type="personal">
    <namePart>Cavanagh, Joseph J. F.</namePart>
    <role>
      <roleTerm authority="marcrelator" type="text">creator</roleTerm>
    </role>
  </name>
  <typeOfResource/>
  <originInfo>
    <place>
      <placeTerm type="text">Boca Raton, FL</placeTerm>
    </place>
    <publisher>CRC Press</publisher>
    <dateIssued>c2007</dateIssued>
    <issuance/>
  </originInfo>
  <physicalDescription>
    <extent>xviii, 900 p. : ill. ; 26 cm.</extent>
  </physicalDescription>
  <note type="statement of responsibility">Joseph Cavanagh</note>
  <note>Includes index.</note>
  <subject authority="lcsh">
    <topic>Digital electronics</topic>
  </subject>
  <subject authority="lcsh">
    <topic>Logic circuits</topic>
    <topic>Computer-aided design</topic>
  </subject>
  <subject authority="lcsh">
    <topic>Verilog (Computer hardware description language)</topic>
  </subject>
  <classification authority="ddc">621.392</classification>
  <recordInfo>
    <recordContentSource authority="marcorg">DLC</recordContentSource>
    <languageOfCataloging>
      <languageTerm authority="iso639-2b" type="code">DLC</languageTerm>
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