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Application-Specific Mesh-based Heterogeneous FPGA Architectures / by Husain Parvez, Habib Mehrez.

By: Parvez, Husain [author.]Contributor(s): Mehrez, Habib [author.] | SpringerLink (Online service)Material type: Text

TextISBN: 9781441979278Subject(s): Engineering | Electronics | Systems engineering | Engineering | Circuits and Systems | Electronics and Microelectronics, InstrumentationAdditional physical formats: Printed edition:: No titleDDC classification: 621.395 LOC classification: TK7888.4TK7895.G36Online resources: Full text available from SpringerLink ebooks - Engineering (2011)

Contents:

Introduction -- State of the Art -- FPGA Layout Generation -- ASIF: Application Specific Inflexible FPGA -- ASIF using Heterogeneous Logic Blocks -- ASIF Hardware Generation -- Conclusion and Future Lines of Research.

In: Springer eBooksSpringerLink ebooks - Engineering (2011)Summary: Low volume production of FPGA-based products is quite effective and economical because they are easy to design and program in the shortest amount of time. The generic reconfigurable resources in an FPGA can be programmed to execute a wide variety of applications at mutually exclusive times. However, the flexibility of FPGAs makes them much larger, slower, and more power consuming than their counterpart ASICs. Consequently, FPGAs are unsuitable for applications requiring high volume production, high performance or low power consumption. This book presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. It describes state-of-the-art techniques for reducing area requirements in FPGA architectures, which also increase performance and enable reduction in power required. Coverage focuses on reduction of FPGA area by introducing heterogeneous hard-blocks (such as multipliers, adders etc) in FPGAs, and by designing application specific FPGAs. Automatic FPGA layout generation techniques are employed to decrease non-recurring engineering (NRE) costs and time-to-market of application-specific, heterogeneous FPGA architectures. Presents a new exploration environment for mesh-based, heterogeneous FPGA architectures; Describes state-of-the-art techniques for reducing area requirements in FPGA architectures; Enables reduction in power required and increase in performance.

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Item type	Current location	Home library	Shelving location	Call number	Status	Date due	Barcode	Item holds
Book	School of Mechanical & Manufacturing Engineering (SMME)	School of Mechanical & Manufacturing Engineering (SMME)	General Stacks	621.395 PAR (Browse shelf)	Available		SMME-1847

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Low volume production of FPGA-based products is quite effective and economical because they are easy to design and program in the shortest amount of time. The generic reconfigurable resources in an FPGA can be programmed to execute a wide variety of applications at mutually exclusive times. However, the flexibility of FPGAs makes them much larger, slower, and more power consuming than their counterpart ASICs. Consequently, FPGAs are unsuitable for applications requiring high volume production, high performance or low power consumption. This book presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. It describes state-of-the-art techniques for reducing area requirements in FPGA architectures, which also increase performance and enable reduction in power required. Coverage focuses on reduction of FPGA area by introducing heterogeneous hard-blocks (such as multipliers, adders etc) in FPGAs, and by designing application specific FPGAs. Automatic FPGA layout generation techniques are employed to decrease non-recurring engineering (NRE) costs and time-to-market of application-specific, heterogeneous FPGA architectures. Presents a new exploration environment for mesh-based, heterogeneous FPGA architectures; Describes state-of-the-art techniques for reducing area requirements in FPGA architectures; Enables reduction in power required and increase in performance.