Development of verification and debugging tool for RTL codes in Verilog HDL using co-simulation with C language model / Hassaan Touheed ,NC Muhammad Afzal Malik , GC Umar Farooq and PC Abbas Ali Mirza
Publisher: Rawalpindi MCS (NUST) 2001Description: 61pSubject(s): UG Projects | TCC-9DDC classification: 621.382,TOU
Contents:
Introduction (Page-7), Digital System Design in Hardware Description Language (Page-9), Hardware Modelling in Programming Language (Page-17), The Sockets API (Page-19), Verilog PLI (Page-23), PLI Routing in Verilog Stimulus (Page-25), PLI Interface in C (Page-32), Using the Routines (page-35), C Functions Behind PLI Routines (Page-40), Cosimulation for Media Engine 0 (Page-44), RLT Debugging and Verification Environment for Micro Engines (Page-50).
| Item type | Current location | Home library | Shelving location | Call number | URL | Status | Notes | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|---|---|---|---|
Project Report
|
Military College of Signals (MCS) | Military College of Signals (MCS) | Reference | 621.382, TOU (Browse shelf) | Link to resource | Available | Almirah No. 94, Shelf No. 1 | MCSPTC-31 |
Total holds: 0
Introduction (Page-7), Digital System Design in Hardware Description Language (Page-9), Hardware Modelling in Programming Language (Page-17), The Sockets API (Page-19), Verilog PLI (Page-23), PLI Routing in Verilog Stimulus (Page-25), PLI Interface in C (Page-32), Using the Routines (page-35), C Functions Behind PLI Routines (Page-40), Cosimulation for Media Engine 0 (Page-44), RLT Debugging and Verification Environment for Micro Engines (Page-50).
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