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V-Holt Verifier (A formal verification tool for combinational circuits) Nirmal Saeed

By: Nirmal Saeed Contributor(s): Ayesha Inam, Aisha Khan Publisher: Islamabad NUST-SEECS 2012Description: 72p. ;ill. ;27cm.+ CD ROMDDC classification: BEE-5 Online resources: Click here to access online

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Item type	Current location	Home library	Shelving location	Call number	Status	Date due	Barcode	Item holds
Project Report	Central Library (CL)	Central Library (CL)		BEE-5 NIR (Browse shelf)	WITHDRAWN		SEECSP01132
Thesis	Central Library (CL)	Central Library (CL)	Thesis	621.3 (Browse shelf)	WITHDRAWN		CL-BP-702

Total holds: 0

Supervisors: Dr. Osma Hasan, Dr. M. Murtaza Khan

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