Switch-level timing simulation of MOS VLSI circuits / by Vasant B. Rao ... [et al.].
Series: Kluwer international series in engineering and computer science: ; Kluwer international series in engineering and computer science: Publisher: Boston : Kluwer Academic Publishers, c1989Description: x, 209 p. : ill. ; 25 cmISBN: 0898383021Subject(s): Telecommunication EngineeringDDC classification: 621.381730724,RAD
Contents:
Introduction (Page-1), Overview Simulation Techniques (Page-7), MOS Network Partitioning and Ordering (Page-27), Switch Level Timing Simulation (Page-93), Simulating Strongly Connected Components (Page-163).
| Item type | Current location | Home library | Shelving location | Call number | URL | Status | Notes | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|---|---|---|---|
Reference
|
Military College of Signals (MCS) | Military College of Signals (MCS) | Reference | 621.381730724,RAD (Browse shelf) | Link to resource | Not for loan | Almirah No.21, Shelf No.5 | MCS801 |
Total holds: 0
Introduction (Page-1), Overview Simulation Techniques (Page-7), MOS Network Partitioning and Ordering (Page-27), Switch Level Timing Simulation (Page-93), Simulating Strongly Connected Components (Page-163).
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