Integrated circuit manufacturability : the art of process and design integration / edited by Jos⥠Pineda de Gyvez, Dhiraj Pradhan.
Publisher: Piscataway, NJ : New York : IEEE Press ; Institute of Electrical and Electronics Engineers, c1999Description: xv, 316 p. : ill. ; 26 cmISBN: 8186308733Subject(s): Integrated circuits -- Testing | Metal oxide semiconductors, Complementary -- Computer-aided design | Telecommunication engineeringDDC classification: 621.3815,INT Online resources: Contributor biographical information | Publisher description | Table of Contents
Contents:
Introduction (Page-1), Defect Monitoring And Characterization (Page-9), Digital CMOS Fault Modeling And Inductive Fault Analysis (Page-43), Functional Yield Modeling (Page-85), Critical Area And Fault Probability Prediction (Page-121), Statistical Methods Of Parametric Yield And Quality Enhancement (Page-157), Architectural Fault Tolerance (Page-217), Design For Test And Manufacturability (Page-269), Testing Solutions For MCM Manufacturing (Page-287).
| Item type | Current location | Home library | Shelving location | Call number | URL | Status | Notes | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|---|---|---|---|
Book
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Military College of Signals (MCS) | Military College of Signals (MCS) | General Stacks | 621.3815,INT (Browse shelf) | Link to resource | Available | Almirah No.33, Shelf No.1 | MCS32607 |
Total holds: 0
Introduction (Page-1), Defect Monitoring And Characterization (Page-9), Digital CMOS Fault Modeling And Inductive Fault Analysis (Page-43), Functional Yield Modeling (Page-85), Critical Area And Fault Probability Prediction (Page-121), Statistical Methods Of Parametric Yield And Quality Enhancement (Page-157), Architectural Fault Tolerance (Page-217), Design For Test And Manufacturability (Page-269), Testing Solutions For MCM Manufacturing (Page-287).
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