A parallel algorithm synthesis procedure for high-performance computer architectures / Ian N. Dunn and Gerard G.L. Meyer.
Series: Series in computer science (Kluwer Academic/Plenum Publishers): Publisher: New York : Kluwer Academic/Plenum Publishers, c2003Description: xi, 108 p. : ill. ; 24 cmISBN: 0306477432Subject(s): Computer architecture | Electronic data processing -- Distributed processing | High performance computing | Parallel algorithms | Parallel programming (Computer science)DDC classification: 004.35,DUN Online resources: Publisher description | Table of contents
Contents:
Introduction (Page-1), Parallel Computing (Page-5), Parallel Algorithm Synthesis Procedure (Page-13), Review of Matrix Factorization (Page-29), Case Study 1: Parallel Fast Givens QR (Page-41), Case Study 2: Parallel Compact WY QR (Page-75), Case Study 3: Parallel Bidiagonalization (Page-89), Conclusion (Page-101),
| Item type | Current location | Home library | Shelving location | Call number | URL | Status | Notes | Date due | Barcode | Item holds |
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Book
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Military College of Signals (MCS) | Military College of Signals (MCS) | General Stacks | 004.35,DUN (Browse shelf) | Link to resource | Available | Almirah No.2, Self No.4 | MCS31030 |
Total holds: 0
Introduction (Page-1), Parallel Computing (Page-5), Parallel Algorithm Synthesis Procedure (Page-13), Review of Matrix Factorization (Page-29), Case Study 1: Parallel Fast Givens QR (Page-41), Case Study 2: Parallel Compact WY QR (Page-75), Case Study 3: Parallel Bidiagonalization (Page-89), Conclusion (Page-101),
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