| 000 | 01088 a2200229 4500 | ||
|---|---|---|---|
| 003 | Nust | ||
| 005 | 20220815093111.0 | ||
| 010 | _a 88030591 | ||
| 020 | _a0898383021 | ||
| 040 | _cNust | ||
| 082 | 0 | 0 | _a621.381730724,RAD |
| 245 | 0 | 0 |
_aSwitch-level timing simulation of MOS VLSI circuits / _cby Vasant B. Rao ... [et al.]. |
| 260 |
_aBoston : _bKluwer Academic Publishers, _cc1989. |
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| 300 |
_ax, 209 p. : _bill. ; _c25 cm. |
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| 490 | 1 |
_aThe Kluwer international series in engineering and computer science ; _vSECS 66. _aVSLI, computer architecture and digital signal processing |
|
| 505 | _aIntroduction (Page-1), Overview Simulation Techniques (Page-7), MOS Network Partitioning and Ordering (Page-27), Switch Level Timing Simulation (Page-93), Simulating Strongly Connected Components (Page-163). | ||
| 650 | 0 | _aTelecommunication Engineering. | |
| 700 | 1 |
_aRao, Vasant B. _997084 |
|
| 830 | 0 |
_aKluwer international series in engineering and computer science ; _982222 |
|
| 830 | 0 |
_aKluwer international series in engineering and computer science. _982222 |
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| 942 |
_cREF _2ddc |
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| 999 |
_c175766 _d175766 |
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