| 000 | 01653 a2200277 4500 | ||
|---|---|---|---|
| 003 | Nust | ||
| 005 | 20221129161303.0 | ||
| 010 | _a 98006335 | ||
| 020 | _a8186308733 | ||
| 040 | _cNust | ||
| 082 | 0 | 0 | _a621.3815,INT |
| 245 | 0 | 0 |
_aIntegrated circuit manufacturability : _bthe art of process and design integration / _cedited by Josā„ Pineda de Gyvez, Dhiraj Pradhan. |
| 260 |
_aPiscataway, NJ : _bIEEE Press ; _aNew York : _bInstitute of Electrical and Electronics Engineers, _cc1999. |
||
| 300 |
_axv, 316 p. : _bill. ; _c26 cm. |
||
| 505 | _aIntroduction (Page-1), Defect Monitoring And Characterization (Page-9), Digital CMOS Fault Modeling And Inductive Fault Analysis (Page-43), Functional Yield Modeling (Page-85), Critical Area And Fault Probability Prediction (Page-121), Statistical Methods Of Parametric Yield And Quality Enhancement (Page-157), Architectural Fault Tolerance (Page-217), Design For Test And Manufacturability (Page-269), Testing Solutions For MCM Manufacturing (Page-287). | ||
| 650 | 0 |
_aIntegrated circuits _xTesting. _9103765 |
|
| 650 | 0 |
_aMetal oxide semiconductors, Complementary _xComputer-aided design. _9103794 |
|
| 650 | 0 | _aTelecommunication engineering | |
| 700 | 2 |
_aPineda de Gyvez, Josā„® _9103795 |
|
| 700 | 2 |
_aPradhan, Dhiraj K. _9103796 |
|
| 710 | 2 |
_aIEEE Circuits and Systems Society. _9103691 |
|
| 856 | 4 | 2 |
_3Contributor biographical information _uhttp://www.loc.gov/catdir/bios/wiley044/98006335.html |
| 856 | 4 | 2 |
_3Publisher description _uhttp://www.loc.gov/catdir/description/wiley037/98006335.html |
| 856 | 4 | 2 |
_3Table of Contents _uhttp://www.loc.gov/catdir/toc/onix07/98006335.html |
| 942 |
_cREF _2ddc |
||
| 999 |
_c178593 _d178593 |
||