000			01304 a2200265 4500
003			NUST
005			20221122123639.0
010			_a 93011984
020			_a0471576794
040			_cNust
082	0	0	_a519,MAZ
100	1		_aMazumder,Pinaki _996432
245	1	0	_aGenetic algorithms : _bFor VLSI design Layout & Test Automation / _cPinaki Mazumder
260			_a India _b Pearson Education, _c1999.
300			_aix, 338 p. : _bill. ; _c24 cm.
440		0	_aWiley finance editions _9103332
505			_aIntroduction (Page-1), Partitioning (Page-37), Standard cell and macro cell placement (Page-69), Macro cell routing (Page-107), FPGA technology mapping (Page-140), Automatic test generation (Page-158), Peak power estimation (Page-227), Parallel implementations (Page-252), Conclusion (Page-295), Glossary (Page-305).
650		0	_aGenetic algorithms.
650		0	_aInvestment analysis _xMathematical models. _9103333
650		0	_aInvestments _xMathematical models. _9103334
856	4	2	_3Contributor biographical information _uhttp://www.loc.gov/catdir/bios/wiley044/93011984.html
856	4	2	_3Publisher description _uhttp://www.loc.gov/catdir/description/wiley037/93011984.html
856	4	2	_3Table of Contents _uhttp://www.loc.gov/catdir/toc/onix03/93011984.html
942			_2ddc _cBK _k519,MAZ
999			_c181057 _d181057