000			01303 a2200241 4500
003			Nust
005			20221125143035.0
010			_a 87023013
020			_a0471624632
040			_cNust
082	0	0	_a621.3815,BAR
100	1		_aBardell, Paul H. _9103629
245	1	0	_aBuilt-in test for VLSI : _bpseudorandom techniques / _cPaul H. Bardell, William H. McAnney, Jacob Savir.
260			_aNew York : _bWiley, _cc1987.
300			_axiii, 354 p. : _bill. ; _c24 cm.
505			_aDigital Testing and the Need for Testable (Page-1), Introduction to Testable Design (Page-17), Pseudorandom Sequence Generators (Page-61), Test Response Compression Techniques (Page-89), Shift Register Polynomial Division (Page-109), Special Purpose Shift Register Circuits (Page-145), Random Pattern Built-in Test (Page-177), Built –in Test Structures (Page-279), Limitations and other Concerns of Random Pattern Testing (Page-314), Test System Requirements for Built-In Test (Page-311).
650		0	_aTelecommunication engineering
700	1		_aMcAnney, William H. _9103630
700	1		_aSavir, Jacob. _9103631
856	4	2	_3Publisher description _uhttp://www.loc.gov/catdir/description/wiley033/87023013.html
856	4	2	_3Table of Contents _uhttp://www.loc.gov/catdir/toc/onix04/87023013.html
942			_2ddc _cBK
999			_c182015 _d182015