000			00926 a2200193 4500
003			0
005			20251111132134.0
040			_c0
082			_a621.382,RAU
100			_aRauf, GC Asad (TCC-6) _9131782
245			_aDesign, simulation and testing of an 8-BIT processor using VHDL coding for CPLDs / _bGC Asad Rauf, GC Shahzad Hamid Javaid & GC Shahzaib Alam Khan , PC Malik Qasim Bashir and NC Hasan Shahzad Zaidi.
260			_aRawalpindi _bMCS _c1999
300			_a133 p.;
505			_aDesign methodologies (Page-1) Programmable logic devices (Page-8) Hardware descriptive languages (Page-23) Levels of abstraction (Page-53) VHDL for design synthesis (Page-63) Processor design (Page-72) Our processor (Page-91) Software engineering and hardware implementation (Page-123).
650			_aUG Projects _998716
651			_aTCC-6 _9131771
700			_aSupervised by Lt Col Dr. Ashraf Masood _9131783
942			_cPR _2ddc
999			_c188630 _d188630