000			01408 a2200253 4500
003			Nust
005			20170207154025.0
010			_a2005054234
020			_a0-471-72092-5 (alk. paper)
020			_a978-0-471-72092-8
035			_a(OCoLC)ocm61500103
035			_aDAW07365004
040			_cNust
082	0	0	_a621.39/2
082	0	0	_a621.392
100	1		_aChu, Pong P.,
245	1	0	_aRTL hardware design using VHDL :(E-Book) _bcoding for efficiency, portability, and scalability / _cPong P. Chu
260			_aHoboken, N.J. : _bWiley-Interscience, _ccop. 2006
300			_axxiii, 669 p. : _bill. ; _c26 cm.
505	0		_aIntroduction to digital system design -- Overview of hardware description languages -- Basic language constructs of VHDL -- Concurrent signal assignment statements of VHDL -- Sequential statements of VHDL -- Synthesis of VHDL code -- Combinational circuit design : practice -- Sequential circuit design : principle -- Sequential circuit design : practice -- Finite state machine : principle and practice -- Register transfer methodology : principle -- Register transfer methodology : practice -- Hierarchical design in VHDL -- Parameterized design : principle -- Parameterized design : practice -- Clock and synchronization : principle and practice.
650		0	_aDigital electronics _xData processing.
650		0	_aVHDL (Computer hardware description language)
651			_a(E-Book)
942			_2ddc _cBK
999			_c191851 _d191851