000			01540 a2200289 4500
003			Nust
005			20220726124212.0
010			_a 2006024358
020			_a0123704901 (pbk. : alk. paper)
020			_a9780123704900
035			_a(OCoLC)70830951
035			_a(OCoLC)ocm70830951
040			_cNust
082	0	0	_a004.22,HEN
100	1		_aHennessy, John L.
245	1	0	_aComputer architecture : _ba quantitative approach / _cJohn L. Hennessy, David A. Patterson ; with contributions by Andrea C. Arpaci-Dusseau ... [et al.].
250			_a4th ed.
260			_aAmsterdam ; _aBoston : _bMorgan Kaufmann, _c2007.
300			_a1 v. (various pagings) : _bill. ; _c24 cm. + _e1 CD-ROM (4 3/4 in.)
505			_afundamentals of Computer Design (Page-1), Instruction Level Parallelism and its Exploitation (Page-66), Limits on Instruction-Level Parallelism (Page-154), Multiprocessors and Thread-Level Parallelism (Page-196),Memory Hierarchy Design (Page-288). Storage Systems (Page-358), APPENDIX A: Pipelining: Basic and Intermediate Concepts (Page A-2), APPENDIX B: Instruction Set Principles and Examples (Page B-2), APPENDIX C: Instruction Set Principles and Examples (Page C-2).
650		0	_aComputer architecture.
700	1		_aArpaci-Dusseau, Andrea C. _994179
700	1		_aPatterson, David A.
856	4	1	_3Publisher description _uhttp://www.loc.gov/catdir/enhancements/fy0665/2006024358-d.html
856	4	1	_3Table of contents only _uhttp://www.loc.gov/catdir/toc/ecip0618/2006024358.html
942			_2ddc _cBK _k004.22,HEN
999			_c194844 _d194844