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010			_a 2003057671
020			_a9812531319
040			_cRCMS _aDLC _bDLC
050			_a621.392 PAD
082	0	0	_a621.392 PAD
100	1		_aT.R. Padmanabhan _92988
245	1	0	_aDesign through Verilog HDL _cT.R. Padmanabhan, B. Bala Tripura Sundari.
260			_a Singapore _bIEEE Press ; _aHoboken, NJ : _bWiley-Interscience, _cc2004.
300			_axii, 455 p. : _bill. ; _c25 cm.
505			_a1.introduction to VLSI design(page 1)2.introduction to verilog(page 11)3.language constructs and conventions in verilog (page 31)4.gate level modeling -1(page 47)5.gate level modeling -2 (page 81)6.modeling at data flow level(page 127)7.behavioral modeling -1(page 159)8.behavioral modeling 2(page 219)9.functions,tasks and user defined premitives(page 273)10.switch level modeling(page 305)11.system tasks,functions and compiler directives(page 339)12.queues,PLAS,and FSMS(page 407)
538			_aShelf # 09, Row # 1, History & Digital Design.
650		0	_aVerilog (Computer hardware description language) _92989
700	1		_aTripura Sundari, B. Bala. _92990
856	4	2	_3Contributor biographical information _uhttp://www.loc.gov/catdir/bios/wiley046/2003057671.html
856	4	2	_3Publisher description _uhttp://www.loc.gov/catdir/description/wiley039/2003057671.html
856	4	2	_3Table of contents _uhttp://www.loc.gov/catdir/toc/wiley032/2003057671.html
942			_2ddc _cBK _h621.392 PAD