| 000 | 00678 a2200145 4500 | ||
|---|---|---|---|
| 999 |
_c23914 _d23914 |
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| 003 | NUST | ||
| 005 | 20170621114414.0 | ||
| 008 | 170621b xxu||||| |||| 00| 0 eng d | ||
| 020 | _a8178085585 | ||
| 040 |
_aDLC _bDLC _cRCMS |
||
| 050 | _a621.392 YAL | ||
| 082 | _a621.392 YAL | ||
| 100 | 1 |
_aSudhakar Yalamanchili _93022 |
|
| 245 | 1 | 0 |
_aIntroductory VHDL: from simulation to synthesis _bfrom simulation to synthesis _cSudhakar Yalamanchili. |
| 260 |
_aUpper Saddle River, NJ : _bPrentice Hall, _c2001. |
||
| 300 |
_a401 p. : _bill. + _e1 computer optical disk (4 3/4 in.) |
||
| 538 | _iShelf # 09, Row # 1, History & Digital Design. | ||
| 650 | 0 |
_aVHDL (Computer hardware description language) _92937 |
|
| 856 | _3Table of Contents Only. | ||
| 942 |
_cBK _k621.392 YAL _2ddc _h621.392 YAL |
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